1. Field of the Invention
The present invention relates to the general field of dielectrically-isolated (DI) high-voltage devices and, more particularly, to a new class of devices which include selective areas of doped silicide used to fabricate high-speed, high-frequency devices.
2. Description of the Prior Art
For many high voltage applications, dielectric isolation is utilized to prevent interaction between adjacent integrated circuit devices formed on a common semiconductor substrate. Basically, dielectric isolation refers to the use of a layer of dielectric material (silicon dioxide, for example) to surround a region, or tub, containing a high-voltage device structure. As long as the reverse breakdown voltage of the dielectric is not surpassed, the high voltage devices will operate properly. One exemplary DI structure is disclosed in U.S. Pat. No. 4,593,458 issued to M S. Adler on June 10, 1986.
In the past, these DI device structures were often limited in the speed of their performance, primarily as a function of the sheet resistance of the material forming the tub region. One solution is to this problem is disclosed in U.S. Pat. No. 3,381,182 issued to C. G. Thornton on Apr. 30, 1968. Thornton teaches a DI structure which includes a silicide layer (MoSi.sub.2, for example) which is disposed to completely surround the dielectric (see FIG. 1c). As proposed by Thornton, this silicide layer thus makes a wide area contact between a buried low resistivity region (the bottom of the tub) and a higher resistivity collector region, thus significantly reducing the collector resistance and increasing the device speed.
Although this silicide layer is adequate in performing this function, there exist many other high-voltage device structures, both bipolar and MOS, which cannot enjoy the same benefits of this silicide wrap-around layer.
Thus, a need remains in the prior art for some means of providing improved speed performance to various devices formed in the high-voltage DI structure.